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AHSANULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY

Department of

Electrical & Electronic Engineering




Prof. Dr. Satyendra Nath Biswas



Designation: Professor

Email: sbiswas.eee@aust.edu

Phone:

Office Extension: 607

Room No: 425

Google Scholar Profile

Scopus Profile

Orcid Profile



Research Interests

  • VLSI Design
  • SoC Design and Testing
  • Video/Image Processing
  • Reconfigurable Computing

Educational Background

  • Ph.D. (EEE) Yamaguchi University, Japan
  • Master of Science (MSc) (EEE) Yamaguchi University, Japan
  • Bachelor of Science (BSc) (EEE) BUET

Honors and Achievements

  • Ministry of Education Japan Scholarship , Yamaguchi University , 1993

Publications

  • Comparative Study and Design of Current Starved Ring Oscillators in 16 nm Technology , IEEE Transactions on Circuits and Systems II, Vol. 64, No. 4, pp. 1098-1102 , 2021
  • An Optimized Tongue Drive System for Disabled Persons , IEEE Instrumentation and Measurement Technology Conference , 2021
  • 6Transistor and 1Memristor based memory Cell , Int. Journal of Reconfigurable and Embedded Systems , 2020
  • A Robust DWT-based Compressed Domain Video Watermarking Technique , International Journal of Image and Graphics , 2020
  • Wallace and Dadda Multiplier design using novel hybrid 3-2 Counter, , IEEE ICAICT Conference , 2020
  • Real Time Intelligent Traffic Light System”, , WSEAS Transactions on Systems , 2020
  • A new model of Dynamic logic circuit with nMOS based keeper , ACTA Universitatis Sapientiae Electrical and Mechanical Engineering , Vol. x, No. x, pp. xx-xx, 2020 (In press). , 2020
  • Low Power Full Adder Design Using PTM Transistor Model , Carpathian Journal of Electronic and Computer Engineering , 2019
  • Characterization of Novel 8T SRAM with Low Leakage and Optimized Area , Carpathian Journal of Electronic and Computer Engineering , 2019
  • Face Identification Based on Discrete Wavelet Transform and Neural Network , International Journal of Image and Graphics , 2019
  • Low level logic fault testing ASIC simulation environment, Integrated Systems, , Design and Process Science (SDPS) International Conference , 2019
  • A High Speed and Low Power 32nm FinFET Dynamic Latch Comparator Design, , IEEE ICASERT Conference , 2019
  • MOSFET-like Carbon nanotube Field Effect Transistor based Full adder design, , IEEE ICASERT Conference , 2019
  • An Energy- Efficient Full-Adder Design Using Pass-Transistor Logic , IEEE ICIET Conference , 2019
  • Design and Analysis of high Efficient Latched Comparator, , IEEE ICASERT Conference , 2019
  • Design and Analysis of Low power, High Speed Latched Comparator for Area Minimization, , IEEE ICIET Conference , 2019
  • Memristor-based High-Speed Memory Cell with Stable Successive Read Operation , IEEE Transaction on Computer aided design of Integrated circuits , 2018
  • On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing , IEEE Transactions on Instrumentation and Measurement , 2018
  • A New hybrid Memory cell based on Four Transistors and one Memristor (4T1M) , International Conference on Computational Advancement in Communication Circuit and System , 2018
  • Low Power Novel 10T SRAM with Stabled Optimized Area , 4th IEEE international Women in Engineering (WIE) Conference on Electrical and Computer Engineering (IEEE WIECON-ECE), , 2018
  • A New Model of High Speed 7T SRAM Cell , International Conference on Computer, Communication, Chemical, Materials and Electronic Engineering , 2018
  • Memristor-based High-Speed Memory Cell with Stable Successive Read Operation , , IEEE Transaction on Computer aided design of Integrated circuits , 2018
  • 7T SRAM Memory cell, , IEEE ICIMIA conference , 2017
  • Low power nMOS based memory cell , IEEE ICIMIA conference , 2017
  • nMOS based Resistive Keeper Circuit for Low Power Dynamic Logic, , IEEE ICIMIA conference , 2017
  • A New Model of Low Power Dynamic Logic Circuit, , IEEE Region 10 Humanitarian Technology Conference , 2017
  • N-FinFET based Resistive Keeper Circuit for Low Power Dynamic Logic , , IEEE ICIMIA conference , 2017
  • A low power Dynamic Logic with nMOS based resistive keeper circuit, , IEEE ICIMIA conference , 2017
  • A high performance Dynamic Logic with nMOS based Resistive Keeper Circuit, , IEEE ISCAIE conference , 2017
  • 4Transistor and 2 Memristor based Memory, , IEEE ISCAIE conference , 2017
  • Automatic Vehicle Number Plate Recognition Using Structured Elements, , IEEE international (ICSPC) Conf. Malaysia , 2016
  • A compact multispectral image capture unit for deployment of dnones, , Proceedings of the IEEE IMTC International Conference , 2016
  • An Algorithm for Generating Prime Implicants, , IEEE IMTC International Conference , 2016
  • A memristor-based 6T1M hybrid memory cell without state drift during successive read, , IEEE ICECE conference , 2016
  • Performance Evaluation and Read Stability enhancement in SRAM bit cell in 16 nm CMOS, , IEEE 5th ICIEV conference , 2016
  • Performance analysis of a memristor-based hybrid memory cell with rapid bidirectional storage capability, , IEEE ICEEICT conference , 2016
  • A short duration voice data recognition using novel fuzzy logic and vector quantization algorithm , IEEE IMTC International Conference , 2016
  • Design a memristor-based hybrid memory cell having faster bidirectional storage operation, , IEEE 5th ICIEV conference , 2016
  • Advanced Encryption Techniques Based on S-Box and Elliptical Curve revisited, , Proceedings of the SDPS International Conference, USA , 2015
  • Digital wavelet transform based image forgery detection using post processing , Proceedings of the SDPS International Conference USA , 2015
  • Designing Elementary-Tree Space Compressors using AND/NAND and XOR/XNOR Combination , IEEE IMTC International Conference , 2015
  • Image Processing Based System for the Classification of Vehicles for Parking Purposes, , IEEE IMTC International Conference , 2015
  • Performance of a prime implicants generation algorithm , Proceedings of the SDPS International Conference USA , 2015
  • Advanced Encryption Techniques Based on Substitution Box with Elliptical Curve , CODEC 2015- International Conference on Computers and Devices for Communication , 2015
  • Designing Elementary-Tree Space Compressors using AND/NAND and XOR/XNOR Combination, , IEEE IMTC International Conference , 2015
  • On System-on-Chip Testing Using Hybrid Test Vector Compression , IEEE Transactions on Instrumentation and Measurement. , 2014
  • Low level logic fault testing ASIC simulation environment , World Journal of Engineering, , 2014
  • Fault detection and test response compaction with array of two input linear logic , Journal of Electrical Engineering , 2014
  • Designing home security and monitoring system based on FPGA , IETE Journal of Technical Review , 2014
  • Elementary tree space compression using combination of nonlinear and linear logic, , 22nd annual int. conference on composites or nano engineering, , 2014
  • New S-Box architecture for advanced encryption standard , The NEWCAS International Conference , 2014
  • Use of Session Initiation Protocol in Multimedia Communications: Evaluation of Server Performance Based on Software Profiling , Applied Cyber-Physical Systems , 2014
  • Image processing based system for the classification of vehicles for parking purpose, , Proceedings of the SDPS International Conference, 2014. , 2014
  • Design and implementation of high-performance master/slave memory controller with microcontroller bus architecture, , Proceedings of the IEEE IMTC International Conference , 2014
  • Elementary tree space compression using combination of nonlinear and linear logic, , 22nd annual int. conference on composites or nano engineering , 2014
  • Energy efficient optimization of wireless embedded sensor networks , World Journal of Engineering, , 2013
  • An automated test system for asymmetric digital subscriber line equipment , World Journal of Engineering, , 2013
  • Response compression in space with cascade of two-input linear and nonlinear logic , World Journal of Engineering, , 2013
  • Fault-tolerance in VLSI systems design using data compression under constraints of failure probabilities–overview and current status , World Journal of Engineering, , 2013
  • Nonlinear mixed logic in space compression using some results on ISCAS 89 Full scan circuits, , 21st annual int. conference on composites or nano engineering , 2013
  • Data compression using mixed cascade of nonlinear logic, , IEEE IMTC International Conference , 2013
  • High speed S-Box architecture for advanced encryption standard , Proceedings of the SDPS International Conference , 2013
  • Designing AMBA based AHD master/slave memory controller, , Proceedings of the SDPS International Conference , 2013
  • Compressed Video Watermarking Technique , IEEE IMTC International Conference , 2013
  • Circuit Architecture test verification based on hardware software co-design with modelsim , IETE Journal of Research , 2013
  • Implementing a Built-in-self-test Environment for cross-baseddigital circuits with Verilog HDL using Principles of Hardware and Software co-design. , World Journal of Engineering, , 2012
  • Cascade of Two-Input Nonlinear Logic in Designing Space Compression Networks in VLSI , World Journal of Engineering, , 2012
  • System on chip design using SCAS benchmark Circuits-An Approach to fault injection and simulation based on Verilog HDL , IETE Journal of Research , 2012
  • Aliasing-Free Space Compaction in VLSI with Cascade of Two-Input OR/NOR Logic , Int. J. of Research and Reviews in Computer Science , 2012
  • Digital Video Watermarking Technique , IEEE IMTC International Conference , 2012
  • ATLANTA and FSIM Simulation in Response Data Compaction of Multi output Digital Circuits with Array of Two input non linear Logic, , Proceedings of the SDPS International Conference, , 2012
  • Session Initiation Protocol in Multimedia Communications-Server Performance by Software Profiling, , SDPS International Conference , 2012
  • Two input linear cascade in space compression , IEEE IMTC International Conference , 2012
  • Sensor Based Home Automation and Security System , IEEE IMTC International Conference , 2012
  • Investigation of the session initiation protocol , IEEE International Conference on Computers and Devices for Communication (CODEC) , 2012
  • Test vector compression Technique in VLSI Circuit , ICAEE International Conference , 2011
  • Two input OR/NOR cascade in Space Compression in VLSI, , ICCE-19 International Conference , 2011
  • Home Control and Security System Design and Implementation , IEEE Int. Conference on Soft Computing and Pattern Recognition , 2011
  • Intellectual property (IP) cores and a logic fault test simulation environment , IEEE IMTC International Conference , 2010
  • RFID for the Optimization of the Public Transportation System , IEEE IMTC International Conference , 2010
  • Hybrid test vector compression in system-on-chip test- An overview and methodology , IEEE International Conference on Computers and Devices for Communication (CODEC) , 2009
  • Fault grading in output merger for space compression in core based system on chips (SoCs), , 28th International IASTED Conference , 2009
  • Designing Space Compressor for System on Chip Testing , International conference on Composites/Nano Engineering (ICCE) , 2009
  • Logic fault test simulation environment for IP core based digital systems , Midwest symposium on circuits and systems , 2009
  • Further studies on improved test efficiency in cores-based system-on-chips using ModelSim verification tool, , IEEE Instrumentation and Measurement Technology Conference , 2009
  • Test vector compression technique in System on Chip , IEEE Instrumentation and Measurement Technology Conference , 2009
  • Low level logic fault testing ASIC simulation environment, Integrated Systems, , Proceedings of the Design and Process Science (SDPS) International Conference , 2009
  • Aliasing-free compaction revisited , IET Circuits, Devices and Systems , 2008
  • A Novel Technique for Input Vector Compression in System-on-Chip Testing, Proceedings of the I , IEEE International Conference on Information Technology , 2008
  • Developing Automated Test System for ADSL Equipment , IEEE Instrumentation and Measurement Technology Conference , 2008
  • Verification of Ethernet IP core MAC design using deterministic test Methodology , IEEE Instrumentation and Measurement Technology Conference, , 2008
  • Further studies of space compression in embedded cores-based system using fault graded output merger, , IEEE Instrumentation and Measurement Technology Conference , 2008
  • Modelsim verification tool in testing core based system on chips, , 27th International IASTED Conference , 2008
  • Testing core based system on chips using modelsim verification tool , 11th SDPS conference on Integrated Design and Process Technology (IDPT) , 2008
  • Software based Self Testing Hybrid Technique for Test Vector Compression, , Proceedings of the 11th SDPS conference on Integrated Design and Process Technology (IDPT), , 2008
  • Hybrid Technique for Test Vector Compression , 11th SDPS conference on Integrated Design and Process Technology (IDPT) , 2008
  • Further studies on zero-aliasing space compression based on graph theory , 24th IEEE Instrumentation and Measurement Technology Conference , 2007
  • Testing analog and mixed-signal circuits with built-in hardware – new approach , IEEE Transactions on Instrumentation and Measurement , 2007
  • Complex ASIC core design using coverage-driven functional verification and reuse methodology, , 10th World Conference on Integrated Design and Process Technology , 2007
  • Designing zero-aliasing space compressors – graph theory approach , 26th IASTED International Conference on Modeling, Identification and Control , 2007
  • VLSI circuit test vector compression technique , IEEE Instrumentation and Measurement Technology Conference , 2007
  • Aliasing-free compaction revisited , 3rd International Conference on Computers and Devices for Communication (CODEC) , 2006
  • Space compactor design in VLSI circuits based on graph theoretic concepts , IEEE Transactions on Instrumentation and Measurement , 2006
  • A software-based method for test vector compression in system-on-a-chip , IEEE Instrumentation and Measurement Technology Conference , 2006
  • A new graph theory technique to design zero-aliasing space compressors, , The World Conference on Integrated Design and Process Technology , 2006
  • An adaptive compressed MPEG-2 video watermarking system , IEEE Transactions on Instrumentation and Measurement , 2005
  • Space compactor design in VLSI circuits based on graph theoretic concepts, , IEEE Instrumentation and Measurement Technology Conference, , 2005
  • A New Approach for Optical Flow Analysis in Sequential Images , International Workshop on Computer Vision, Pattern Recognition and Image Processing, Germany , 1998
  • Motion Analysis from Image Sequences using Wavelet Transform", , International Conference on Audio, Video, Image Processing and Intelligent Applications , 1998
  • A method for motion compensation of moving objects and its application to frequency analysis of pharyngeal pulsation of Nematode, Caenorhabditis elegans , Int. Journal of Bio-technology , 1998
  • Investigation of Dynamic Behaviors in Periodic Organs of C. elegans by sequential Image Analysis , 11th. International Conference on C.elegans , 1997
  • Extraction of Dynamic Characteristics in C. elegans Behaviors by VTR Picture Analysis , 11th symposium of Biological and Physiological Engineers , 1996
  • A phenomenological model describing pharyngeal pulsing in nematode Caenorhabditis elegans anesthetized by alcohol , Research Communications in Chemical Pathology and Pharmacology , 1996
  • A method for presenting motion compensation images for pharyngeal pulsing frequency analysis of moving Nematode , Meeting of Chugoku Branch Electrical and Related Engineers , 1995
  • Instantaneous current vector control-based soft-switched high-frequency resonant inverter using static induction transistors for induction-heating power supply , IEEE Conference on Power Electronics and Drive System (PEDS '95) , 1995